========================[ INTRODUCTION              ]=========================
Physical address -- address actually being manipulated.
Virtual/logical address -- address generated by user programs.

High-level memory allocation -- how we give memory to a process. First two are forms of contiguous mapping.
1) Multiple-partition method: each partition gets one process. done.
2) Fixed-partition scheme: keep track of what memory is open, try to fit processes into holes.
3) Paging: permits physical address space of a process to be non-contiguous. Best because different processes can be all be in memory.

Theoretically, a VM is a per-process fetch/store:
* process => fetch : (address => data)        (returns)
* process => store : (address, data => .)     (mutates)


========================[ HARDWARE STRUCTURES       ]=========================
Translation lookaside buffer (TLB) -- associative cache that maps V => P.
Memory-management unit (MMU) -- complete unit that maps V => P. Normally uses TLB; if uncached, utilizes slower calculation using page directory/table. 
Frame table -- allocation status of frames and request/free.

Sounds all good. But how do we do it in hardware? (Note: Software possible but TRICKY!)
* Page table entry (32-bits) -- 10-bit index into page directory to find page table, 10-bit index into page table to find page, add 12-bit offset (which addresses 4028 bytes.)
* Page directory (4-kilobytes) -- page_directory[page_table_index] = page table to use. 
* Page table (4-kilobytes) -- page_table[page_number] + page_offset = physical_address )
Note, for page directories and page tables, the bottom 12-bits are for permission flags. (They're assumed to be 0'd by the memory address.) Only the top 20-bits are used to deduce address.

Internal structure / Hardware support -- how do we want to store the page tables?
1) Set of registers as the page table -- just use arithmetic to translate. Satisfactory if page table is small.
2) Page-table base register (PTBR) -- points to the page table we're currently manipulating. Changing page tables only requires changing one register. Slow access times though.
3) Translation look-aside buffer (TLB) -- an enhancement to PTBRs. Associative, high-speed memory that maps keys to values. Degrades to (2) on misses. (p283)
* Set automatically by activating new page directory. (See L16.)
** Implementation details in dual-view memory model. (L16,p37).


========================[ MISCELLANEOUS             ]=========================
Page fault -- Hardware generates a page fault for page accesses where:
* the page corresponding to the requested address is not loaded in memory.
* the page corresponding to the memory address accessed is loaded, but its present status is not updated in hardware.

Speed hacks:
* Copy-on-write (COW) -- on <fork>, marks shared pages as read-only. On write, maps in extra page, marks as read-write.
* Zero-fill on demand (ZFOD) -- many pages are blank (bss, new heap, new stack). Have one system-wide all-zero frame. Everyone points to it. Writes cause new map.

Page replacement -- eventually we run out. Page to disk.